Intel Data Centre CTO: Moore's Law is far from over
Steve Pawlowski says when Intel can no longer scale in two dimensions, it will scale in three
The Big Data battle
Many of the new features that have been introduced with the E5 family of processors are aimed at tackling Big Data. Pawlowski said that, as Intel's CTO for the data centre, he is constantly asked about the cloud and where Big Data should be stored, but he warned that “one cloud does not fit all”.
For example, he said that the computing centre at CERN generates more raw data in a minute than most organisations do in a year, so they have to do a lot of filtering up front. “They could be throwing away good science because they simply don't have the capability to store that volume of data,” he said.
At the other end of the spectrum, oil and gas companies that take seismic measurements in the field may want to keep that data forever because, as machines become more powerful and the fidelity of the models improves, they can use it to find oil where they couldn't see it before.
Pawlowski said that data will continue to drive everything that Intel does. However networks are going to have to become more sophisticated and more distributed in terms of their control structure, in order to deal with some of the challenges posed by Big Data.
“Big Data has me worried,” he said. “I've had some conversations with the military where their soldiers are in the field. They're actually part of the network – think of them as the end device. They're collecting data about the battle situation, and they're all being integrated into a larger collection of information, giving commanders in the rear echelons a realistic view of the field, so they can give the appropriate data to the soldiers in order to help them do their job.
“If you happen to lose a soldier you lose a point of the network, you've got to reconfigure and re-heal that network. That all has to be done ad hoc. There isn't going to be some grand node manager that figures that out, because those things are going to be so remote, you've got to be able to have some intelligence between those devices to be able to handle it. Having something this centralised would just not scale to where these things are going to go in time.”
Xeon vs RISC
Pawlowski believes that, with the improvements in Intel's latest processors, Xeon is in a strong position to step up its attack on the RISC-based Unix market. RISC, or reduced instruction set computing, is a CPU design strategy based on the philosophy that simplified instructions can provide higher performance.
“I was in the old RISC/CISC wars, where everybody said CISC (complex instruction set computing) is dead, RISC is going to take over,” he said. “With Moore's Law, and the ability to put more capability on a given die area, there is no reason why an architecture like x86 doesn't have the robustness to continue to support that. The capability and the reliability is there.
“So now we're able to offer greater RAS functionality for a lower cost than what people were used to in the high-end space,” he added. “When you tie in performance with reliability, it now becomes a very compelling argument as a RISC replacement.”
He said that Xeon chips have become much more capable in terms of overall raw performance, and the differentiation between Xeon and RISC in terms of features is also fading away. Where, traditionally, there would have been trade-off between desktops and servers, now Intel is able to build server-specific parts and client-specific parts onto the same chip.
“Xeon is an extremely capable part for mission critical systems,” said Pawlowski. “We're building more and more of that capability going forward because people are willing to pay for it and, in the server space, we're able to differentiate in a different way from in the core space.”
Steve Pawlowski has worked for Intel since 1982 and led the design of the first Multibus I Single Board Computer based on the 386 processor. He was a lead architect and designer for Intel's early desktop PC and high performance server products, and was the co-architect for Intel's first P6 based server chipsets. As well as being Digital Enterprise Group CTO, he is also an Intel Senior Fellow.