Is NAND flash about to hit a dead end?
Some believe the ubiquitous chips have five years left - at most
By Lucas Mearian | Computerworld US | Published: 11:13, 06 February 2010
When IM Flash Technologies (IMFT) announced this week that its manufacturing a 25-nanometer (nm) NAND flash chip, the company also admitted that shrinking the technology much further may not be possible because of problems with bit errors and cost.
If that turns out to be true, one of the basic building blocks used for storage in solid-state drives (SSDs) and memory cards may be nearing a dead end.
"I think in the next four years or five years, it's probably going to be the case" that NAND will no longer be the storage medium, said Gregory Wong, a flash memory analyst with market research firm Forward Insights.
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"Everybody's looking at alternatives." NAND flash memory has been the single biggest change to drive technology in recent several years, with the storage medium showing up in data centres, high-end laptops like Apple's MacBook Air and in memory cards in mobile devices.
Apple has largely driven the adoption rate with its use of NAND flash in its popular iPods and iPhones, sales of which helped drive flash memory costs down through mass production.
iSuppli forecasts that the global flash memory card market will grow from 530 million units this year to 9.5 billion units by 2013, a market that will then be worth $26.5 billion.
The market for high-capacity memory chips has a lot of room to grow, according to iSuppli, largely because of the rise of smartphones. The more features they offer, whether it's touch screens, wireless Internet access or video capabilities, the more storage they need.
"As we move to high-definition video, that's going to require higher storage capacities," said Wong. "The issue, of course, is ... do you really need HD video on a tiny screen? No, but companies will use HD as a way to differentiate themselves."
For example, Samsung, the world's largest NAND flash memory maker, just released a new 64GB moviNAND embedded chip and 32GB microSD removable memory card for mobile devices. Both were created with its new 30nm lithography technology.
Steve Weinger, senior manager for NAND flash marketing at Samsung Semiconductor, said mobile phone video capabilities and the desire to store a never-ending stream of applications, movies, television shows and video clips from sites like YouTube.com is driving chip development and a 34% annual growth in sales. In fact, NAND flash chip memory has doubled in capacity in a little more than a year, he said.
"You could eventually have in the palm of your hand, all your movies, your pictures and everything else," he said. "I recently watched a football game on my iPhone with the DirectTV application. It was really crystal clear."
The problem, Weinger said, is that it's becoming difficult to make NAND flash memory denser.
Currently, the 25nm lithography being used by IMFT, a joint venture of Intel and Micron, is the smallest NAND production technique in existence. And an intel spokesman was cautious about how much smaller NAND flash memory can reliably get. That's important because smaller chips means more capacity in the same amount of space.
"The challenge of stepping down in lithography is to continue to provide equivalent performance... as previous products," Troy Winslow, director of NAND marketing at Intel, said in an interview with Computerworld . "Those were challenges we were able to overcome with this generation. But looking into the next couple of generations, we do recognize materials and process technology will have to change as obstacles mount."
Intel is already approaching atomic size with its lithography technique. Lithography is the process of creating cells and transistors in silicon, which are used to store bits of data. The smaller they are, the more data that can fit on a single NAND flash chip. At 25nm, the cells in silicon are 3,000 times thinner than a human strand of hair. And at that level inter-cell electrical interference becomes a tougher obstacle to tackle.
According to Michael Yang, a senior analyst for memory and storage with iSuppli, anything smaller than 20nm lithography is uncharted territory for NAND flash.
"Unless it can be proven that [10-19] nanometer or lower is possible with NAND, it will be a crossroads for a new memory technology," Yang wrote in an e-mail response to Computerworld .
In addition, the number of electrons that can be stored in the memory cell decreases with each generation of flash memory, making it more difficult for the cells to reliably retain data, according to Wong.
Multi-level cell NAND, the most common type of flash memory used in consumer products, is in the midst of a transition from storing two bits of data per cell to storing three and four bits per cell.
But additional bits per cell mean additional programming at the controller level order to ensure that each bit is accurately placed, Wong said. While programming for single-level cell (SLC) NAND is relatively simple, as only one bit can be placed in a cell, programming for two-bit and three-bit multi-level cell (MLC) NAND doubles or triples the coding required.
Increasing the number of bits per cell is not always the best answer. When IMFT released its 25nm NAND chip, the company's spokesman said in a Computerworld interview that the company had dropped production of a not-yet shipping three-bits-per-cell MLC NAND product because of reliability issues. That technology, announced last August , used IMFT's 34nm lithography process and represented an 11% reduction in NAND flash size.
"The major drawback of three-bit-per-cell technology is that it comes at the expense of performance and reliability," Kevin Kilbuck, director of NAND marketing at Micron, said.
Although IMFT still hopes to resurrect the three-bit-per-cell technology using the 25nm lithography process, Kilbuck said it's already eyeing technologies other than the floating-gate transistor technology now in use to continue down the path toward smaller, denser data storage hardware. Among those technologies are charge trap flash and phase-change memory. The company is also considering 3D-cell NAND, which involves stacking cells atop one another.
"It's just something we're looking at to extend the life of the NAND cell itself," Kilbuck said. "If we do end up going that route, we can leverage our DRAM process technology and cell technology, since DRAM has been utilizing a 3D-cell with some fine geometries. The goal is to keep scaling so we can stay ahead in cost."
According to Forward Insights, as lithography techniques shrink, bit errors increase, a problem that's compounded by the move toward three-bit and four-bit per cell MLC NAND. Higher bit error rates require more error correction code [ECC] in the flash memory to detect data errors and correct them.
Traditional ECC, however, requires code redundancy and data read latency as the number of errors that must be corrected goes up, according to Forward Insights.
One technology several non-volatile memory companies are exploring is Resistive Random-Access Memory (RRAM). Instead of using silicon as a resistive material, RRAM uses a filament or conduction path in the silicon.
Wong said RRAM technology may have an advantage over other emerging non-volatile memories because it has a lower voltage for programming than phase-change memory and it could have a memory cell size comparable to NAND. "In other words, it is a potentially scalable technology," Wong said.
"There's no clear winner among the up-and-coming technologies, but with stackable 3D RRAM there's a lot of advantages," Wong said. "The industry is quite innovative so [it'll] find some ways to extend NAND. And when it is not possible to scale, an alternative technology will be in place."